A memory cell array of, for example, a read-only memory (hereinafter, referred to as "ROM") comprises a plurality of memory cells arranged in plural rows and plural columns. Plural word lines extend along the rows of the memory cells, and plural bit lines extend along the columns of the memory cells. Each memory cell has its gate connected to a corresponding word line, its source grounded, and its drain connected to a corresponding bit line. To read data from an addressed (or a selected) memory cell, a bit line to which the addressed memory cell is connected is set a predetermined voltage, and a word line to which the addressed memory cell is connected is set at a word line voltage.
Generally, a memory cell of storing one-bit data has one transistor (or one cell transistor). A threshold voltage of the transistor is set at a high or low level so that the memory cell stores one-bit data. But, the memory cell can store one bit of data at a time. To store a great amount of data, the memory cell array needs to have more memory cells in proportion to the amount of data to be stored, causing its chip size to become large inevitably.
To manufacture an integrated circuit memory device which can store a large amount of data without increasing its chip size, it has recently been proposed that two bits of data can be stored in one memory cell. Such a memory cell is called "multi-level memory" or "multi-bit memory". Various types of multi-bit memories may be provided. In one type, the gate length or gate width of the transistor of each memory cell is changed so that the current flowing when the memory cell is selected may be set at various values. In another types, the dose of impurity ions injected into the MOS transistor of each memory cell is changed so that the threshold voltage of the MOS transistor may be set at various values. Thus, each memory cell of the multi-bit memory device can store two or more bits of data when set in two or more states. The multi-bit memory device has therefore its increased storage capacity.
FIG. 1 shows a relationship between word line voltages and threshold voltage distributions in accordance with multi-bit data states in case that one memory cell stores two-bit data. Each memory cell of, for example, multi-bit ROM has one of four different threshold voltages Vth0 to Vth3. The threshold voltages Vth0 to Vth3 have the relationship of Vth0&lt;Vth1&lt;Vth2&lt;Vth3. Any memory cell having a threshold voltage Vth0 will be identified as a memory cell M00, any memory cell having a threshold voltage Vth1 as a memory cell M01, any memory cell having a threshold voltage Vth2 as a memory cell M10, and any memory cell having a threshold voltage Vth3 as a memory cell M11. The memory cells M00, M01, M10 and M11 are assumed to store data "00", "01", "10" and "11", respectively.
FIG. 2 is a diagram showing a voltage variation applied to a word line during a data reading operation. With reference to FIGS. 1 and 2, a data reading operation of a memory cell of storing two bits of data will be described below.
First, a word line connected to a selected (or an addressed) memory cell of storing two-bit data is driven at a first word line voltage V.sub.WL0, which has a middle voltage between Vth0 and Vth1, and then whether a current (or a cell current) flows through the selected memory cell is detected by a sensing circuit (180, refer to FIG. 5). And then, after a second word line voltage V.sub.WL1 higher than the first word line voltage V.sub.WL0 is applied to the word line, whether a cell current flows therethrough is checked thereby. Finally, a third word line voltage V.sub.WL2 higher than the first and second word line voltages V.sub.WL0 and V.sub.WL1 is applied to the word line, and then whether a cell current flows therethrough is also detected thereby. As described above, in case that the selected memory cell stores two-bit data (that is, one of "00", "01", "10" and "11"), three sensing operations (or three read-out operations) are in turn performed by use of different word line voltages V.sub.WL0, V.sub.WL1 and V.sub.WL2, and then results thus sensed are logically made up. By such a set of procedures as set forth above, the data reading operation has been finished.
FIG. 3 is a circuit diagram showing a sensing structure of the prior art associated with one multi-bit memory cell in an integrated circuit memory device 10 according to the prior art. The sensing structure of FIG. 3 is disclosed in U.S. Pat. No. 5,761,132 entitled "INTEGRATED CIRCUIT MEMORY DEVICES WITH LATCH-FREE PAGE BUFFERS THEREIN FOR PREVENTING READ FAILURES", and thus description thereof is omitted. FIG. 4 is a timing diagram for describing a data reading operation according to the prior art. A data reading operation of the integrated circuit memory device 10 will be described with reference to FIGS. 3 and 4.
As set forth above, the data reading operation is completed by performing three read-out operations sequentially. Each of the three read-out operations is performed according to a set of bit line precharge, sensing and discharge periods of time. Before a first read-out operation is performed, bit line precharge and discharge signals Pbpre and Pbdis remain at a high level (i.e., a power supply voltage Vcc level) and a bias voltage Vbiasi is at a predetermined voltage level between Vcc and 0V. This forces the bit line BL and a node Ns (hereinafter, referred to as "a sensing node") to be discharged at the ground voltage.
At a bit line precharge period of time of a first read-out operation, the signal Pbpre goes to a low level (i.e., the ground voltage level) from the high level, and the bias voltage Vbiasi continues to be maintained at the predetermined voltage level. This enables a bit line pass transistor 12 and a bit line precharge transistor 14 to be turned on, so that current from the turned-on transistor 14 is supplied through the bit line pass transistor 12 onto a bit line BL. That is, the bit line BL is precharged at a desired voltage (or a precharge voltage).
At a bit line sensing period of time of the first read-out operation, a voltage level of the signal Pbpre becomes transient between the high level and the low level, as known in FIG. 4. Current (or sensing current) from the bit line precharge transistor 14 switched on according to the signal Pbpre is supplied onto the bit line BL through the bit line pass transistor 12. A potential of the sensing node Ns is changed according to an "ON"/"OFF" state of the memory cell MC. The potential of the sensing node Ns thus changed (that is, read-out data) is inverted by a PMOS transistor 18, and is outputted through a column selection circuit 20.
Successively, at a bit line discharge period of time thereof, the signals Pbpre and Pbdis become the high level and the bias voltage Vbiasi continues to be maintained at the previous set voltage, so that the bit line BL and the sensing node Ns become discharged at the ground voltage. The first read-out operation has been completed by sequentially performing such a set of procedures as described above. Second and third read-out operations are performed equally to the first read-out operation, and description thereof is thus omitted.
When the bit line precharge operation is performed, however, a voltage on the gate of the bit line pass transistor 12 is boosted over the bias voltage Vbiasi in a moment at an initial period of time of the bit line precharge operation, as illustrated in FIG. 4. This is because the gate of the bit line pass transistor 12 is coupled both with the bit line BL (Cb in FIG. 3) and with the sensing node Ns (Cs in FIG. 3). Since the bias voltage Vbiasi becomes elevated over a desired voltage, the bit line BL is precharged over a desired voltage. In case that the memory cell MC is at the "ON" state during one of the read-out operations, a time in which the bit line BL and the sensing node Ns are developed is elongated, as illustrated by a dot line in FIG. 4. As a result, a sensing speed (or data reading speed) of the integrated circuit memory device 10 becomes dropped, and in a worst case, the data reading operation is failed. Accordingly, a reliability of the integrated circuit memory device 10 declines.